The present invention relates to a semiconductor memory device, and more particularly, it relates to noise reduction and operation speed increase for a DRAM (dynamic random access memory) having a hierarchical bit line architecture.
Recently, an embedded-DRAM is required to have a high degree of integration for realizing an SOC (system-on-a-chip) at low cost. It is a memory cell array including memory cells and a column of sense amplifiers that occupies most of the memory area. In order to realize the high degree of integration, the area of the memory cells has been reduced by refinement technique for a memory capacitor using a memory cell transistor and a high dielectric constant insulating film.
On the other hand, the size reduction of a column of sense amplifiers has not been proceeded as much as that of memory cell transistors. This is for the following reason: Although a sense amplifier is required to accurately amplify a small signal read from a memory, when the size of transistors included in the sense amplifier is reduced, the electric characteristics are varied among the transistors, resulting in degrading the performance. Therefore, it is indispensable for reducing the memory area to increase the number of memory cells connected to one bit line so as to relatively reduce the number of sense amplifiers included in the memory cell array.
As a technique to reduce the number of sense amplifiers included in a memory cell array, hierarchical bit line architectures are disclosed in U.S. reissued Pat. No. RE33694 and Japanese Laid-Open Patent Publication No. 6-349267. For example, in the hierarchical bit line architecture disclosed in the latter publication, one global bit line pair is connected to a plurality of local bit line pairs through plurality of selecting means, and the global bit line pair is formed in a layer upper than the layer of the local bit line pairs.
The number of memory cells that can be connected to one bit line is determined depending upon the magnitude of a potential difference (sensing signal) ΔV caused between a bit line BL and its complementary bit line /BL when data of a memory cell is read out to the bit line BL. When the power supply voltage of the array is indicated by Vdd, parasitic capacitance per global bit line is indicated by Cbm, parasitic capacitance per local bit line is indicated by Cb1 and capacitance of a memory cell capacitor is indicated by Cs, the absolute value of the sensing signal ΔV is represented as follows:|ΔV|=(Vdd/2)/((Cb1+Cbm)/Cs+1)
At this point, it is assumed that a hierarchical bit line architecture includes one global bit line and N local bit lines formed in a layer lower than the layer of the global bit line. In this case, as far as Cbm<N×Cb1, a sensing signal can be made larger than in a non-hierarchical bit line architecture while increasing the number of memory cells connected to one bit line by N times (namely, while reducing the number of sense amplifiers to 1/N).
In a DRAM having a stacked capacitor structure, the parasitic capacitance Cbm corresponds to a sum of parasitic capacitance between a global bit line and a surrounding general interconnect conductor and gate capacitance of a sense amplifier portion. On the other hand, the parasitic capacitance Cb1 includes parasitic capacitance between a local bit line and upper/lower electrodes of a memory capacitor that are formed ultimately close to the local bit line by a special process rule, junction capacitance of a memory cell transistor, overlap capacitance between the local bit line and a word line, and the like. Therefore, in general, Cbm<Cb1.
Furthermore, in a sub-100 nm embedded-DRAM process more refined, there is a condition satisfying Cbm<N×Cb1, and hence, when a hierarchical bit line architecture is employed, a sensing signal capable of a stable operation can be secured while reducing the number of sense amplifiers.
FIG. 16 is a circuit diagram for showing the configuration of a conventional semiconductor memory device. FIG. 17 is a timing chart for showing a read operation of the semiconductor memory device of FIG. 16. The operation of the semiconductor memory device of FIG. 16 will now be described with reference to FIG. 17.
At time ta, precharge is terminated by setting a precharge control signal line PR to a ground voltage VSS. At time tb, a voltage of hierarchical switch control signal lines BSa<1:3> and BSb<1:3> (wherein, for example, BSa<1:3> indicates BSa<1> through BSa<3>) connected to hierarchical switches 31a through 33a and 31b through 33b other than hierarchical switches 30a and 30b for mutually connecting a local bit line and a global bit line of a block B0 to be accessed is set to the ground voltage VSS.
Thereafter, at time tc, a word line WL<n> is set to a boosted voltage VPP, and data is read on a bit line from a memory capacitor of a memory cell (charge sharing is performed). Then, at time td, a sense amplifier control signal line SAE is set to an array voltage VDD for starting amplification by a sense amplifier 12, so as to maximize a voltage between global bit lines BLm and /BLm.
At time te, the word line WL<n> and the sense amplifier control signal line SAE are set to the ground voltage VSS for turning off the sense amplifier 12, so as to activate all the hierarchical switch control signal lines BSa<0:3> and BSb<0:3> for starting the precharge. Thereafter, at time tf, the precharge control signal line PR is set to the boosted voltage VPP so as to start bit line precharge.
In such an operation, however, noise on the bit lines is larger than in a non-hierarchical bit line architecture, and hence, the operation characteristics are disadvantageously degraded as follows:
First, in turning off the hierarchical switches of the blocks not accessed at the time tb, coupling derived from a gate-source capacitance of a transistor included in each hierarchical switch causes common mode noise for lowering a bit line precharge level. This is noise peculiar to the hierarchical bit line architecture. In the hierarchical bit line architecture including four local bit lines per global bit line as shown in FIG. 16, three hierarchical switch transistors cause the coupling noise. The influence of this noise is more serious as the number of local bit lines is increased.
Secondly, noise from adjacent bit lines derived from side coupling capacitance with adjacent bit lines is caused during a period of the charge sharing when the data is read out to one of the bit lines from the memory capacitor with the word line activated at the time tc and during the amplification performed by the sense amplifier after the time td. In the hierarchical bit line architecture, the ratio of the side coupling capacitance to total bit line capacitance is larger than in the non-hierarchical bit line architecture.
A local bit line (corresponding to a global bit line in the non-hierarchical bit line architecture) has a large capacitance component including the parasitic capacitance with upper/lower electrodes of a memory capacitor formed ultimately close by the special process rule, the junction capacitance of a memory cell transistor and the overlap capacitance with a word line, and has relatively small coupling capacitance with an adjacent bit line. On the other hand, in a global bit line formed in an upper layer, the coupling capacitance with another bit line adjacent in the vicinity of a minimum pitch is dominant, and the ratio of the adjacent bit line capacitance to the total bit line capacitance is relatively large. As a result, the hierarchical bit line architecture is easily affected by the noise from adjacent bit lines.
In the design of a semiconductor memory device employing the hierarchical bit line architecture, the goal is set at increasing the number of memory cell transistors connected per bit line as much as possible for minimizing the area of a memory cell array. However, it is indispensable to solve the noise problem peculiar to the hierarchical bit line architecture because a detected signal is otherwise small.
Furthermore, in order to reduce the area of a memory cell array, a memory cell transistor is used as a hierarchical switch transistor. Since a portion of the memory cell array disposed beneath a first metal layer is laid out by using the special process rule, periodical arrangement of memory cells is necessary for easing the fabrication particularly in the sub-100 nm embedded-DRAM process (stacked capacitor type). (If any hierarchical switch is disposed against the periodicity of the arrangement, it is necessary to provide a dummy cell on a boundary between a memory cell and the hierarchical switch, and area overhead cannot be avoided.)
In a conventional memory cell transistor, for improving the characteristic for keeping capacitor charge, the source/drain are made of a non-silicide material, the contact resistance is as large as several kΩ or more, and the on current characteristic is sacrificed. Therefore, it is difficult to use such a transistor as a hierarchical switch, which is required to rapidly send charge between a global bit line and a local bit line.
In an embedded-DRAM employing the sub-100 nm process, what is called a “full metal memory cell” including the source/drain of a memory cell transistor made of salicide and a contact made of a metal material such as tungsten is practically used, and the on current characteristic of the memory cell transistor is improved. Accordingly, a memory cell transistor can be used as a hierarchical switch.
However, there is speed overhead derived from use of a hierarchical switch although it is small. In particular, in application where rapid random operation performance is required, there is a demand for a hierarchical bit line architecture in which the speed overhead is reduced and the circuit area is minimized.